1. Field of the Invention
The present invention relates to a memory.
2. Description of the Background Art
In general, volatile and nonvolatile memories are known as semiconductor memories. A DRAM (dynamic random access memory) is known as the nonvolatile memory, and a flash EEPROM (electrically erasable and programmable read only memory) is known as the nonvolatile memory. The DRAM and the flash EEPROM, which can be highly integrated, are widely employed.
FIG. 58 is an equivalent circuit diagram showing the structure of a memory cell 103 of a conventional DRAM. FIG. 59 is a sectional view showing the structure of a trench-type capacitor 102 employed for the conventional DRAM. Referring to FIG. 58, the memory cell 103 of the conventional DRAM serving as a nonvolatile memory is formed by a selection transistor 101 and the capacitor 102. The capacitor 102 stores information of the memory cell 103 as charges. In order to read information from the memory cell 103, a word line WL rises to bring the selection transistor 101 into an ON state. Thus, a cell capacitance Ccell and a bit line capacitance Cb1 are capacitively coupled with each other. Therefore, a bit line potential depending on the quantity of the charges stored in the memory cell 103 can be read.
In the memory cell 103 of the conventional DRAM having the aforementioned structure, an upper electrode 102a, a lower electrode 102c and a dielectric film 102b forming the trench-type capacitor 102 are longitudinally extended as shown in FIG. 59, in order to ensure the cell capacitance Ccell of the capacitor 102 also when the same is refined. If refinement further progresses, however, it is difficult to ensure the capacitance of the capacitor 102 also when employing the trench structure shown in FIG. 59. In other words, high integration of the DRAM resulting from reduction of a design rule approaches to the limit.
In the flash EEPROM (hereinafter referred to as a flash memory) serving as the nonvolatile memory, a memory cell of a CHE (channel hot electron) system such as a stacked or split gate memory cell is limited in refinement of the channel length. In a memory cell of an FN (Fouler-Nordheim) write system such as a NAND memory cell, the limit of refinement is equivalent to that of a logic transistor. However, the flash memory requires a high voltage of 15 V to 20 V for operations, and if the power supply voltage for the logic transistor is reduced, efficiency for forming the high voltage of 15 V to 20 V from the low power supply voltage is reduced. Therefore, power consumption is increased and the area of a charge pumping part is also increased, to disadvantageously hinder refinement.
A ferroelectric memory is known as one of recently noted nonvolatile memories. The ferroelectric memory utilizes pseudo capacitance change resulting from the direction of polarization of a ferroelectric substance as a memory element. The ferroelectric memory, capable of rewriting data at a high speed with a low voltage in principle, is spotlighted as an ideal memory having the advantages of the high speed and the low voltage of the DRAM as well as the advantage of nonvolatility of the flash memory.
Memory cell systems for a ferroelectric memory are roughly classified into three types of systems, i.e., a one-transistor one-capacitor system, a simple matrix system and a one-transistor system. FIG. 60 is an equivalent circuit diagram showing a memory cell 113 of a one-transistor one-capacitor ferroelectric memory. FIG. 61 is an equivalent circuit diagram showing a memory cell array of a simple matrix ferroelectric memory. FIG. 62 is a hysteresis diagram for illustrating operations of the simple matrix ferroelectric memory, and FIG. 63 is a hysteresis diagram for illustrating disturbance in the simple matrix ferroelectric memory. FIG. 64 is an equivalent circuit diagram showing a memory cell 131 of a one-transistor ferroelectric memory, and FIG. 65 is a hysteresis diagram for illustrating operations of the one-transistor ferroelectric memory. FIG. 66 is an equivalent circuit diagram for illustrating a voltage application state in writing of the one-transistor ferroelectric memory shown in FIG. 64, and FIG. 67 is an equivalent circuit diagram for illustrating a voltage application state in a standby state of the one-transistor ferroelectric memory shown in FIG. 64.
As shown in FIG. 60, the memory cell 113 of the one-transistor one-capacitor ferroelectric memory is formed by a selection transistor 111 and a ferroelectric capacitor 112, similarly to that of the DRAM. The memory cell 113 is different from that of the DRAM in the ferroelectric capacitor 112. In operation, a word line WL rises for bringing the selection transistor 111 into an ON state. Thus, a capacitor capacitance Ccell of the ferroelectric capacitor 112 is connected with a bit line capacitance Cb1. Then, a plate line PL is pulse-driven for transmitting charges in a quantity varying with the direction of polarization of the ferroelectric capacitor 112. The ferroelectric memory reads data as the voltage of the bit line BL, similarly to the case of the DRAM.
In the one-transistor one-capacitor ferroelectric memory having a structure similar to that of the DRAM, refinement of the ferroelectric capacitor 112 is limited. Therefore, the ferroelectric memory is limited in high integration similarly to the DRAM.
The simple matrix ferroelectric memory is now described with reference to FIGS. 61 to 63. As shown in FIG. 61, each memory cell 121 of the simple matrix ferroelectric memory is constituted by a ferroelectric capacitor 122 consisting of a word line WL and a bit line BL formed to extend in directions intersecting with each other and a ferroelectric film (not shown) arranged between the word line WL and the bit line WL. An end of the ferroelectric capacitor 122 is connected to the word line WL while another end thereof is connected to the bit line BL. The simple matrix ferroelectric memory, reading a potential resulting from capacitive coupling between the bit line BL and the ferroelectric capacitor 122, must ensure capacitances similarly to the DRAM. In the simple matrix ferroelectric memory, however, each memory cell 121 is formed by only the ferroelectric capacitor 122 with no selection transistor, whereby the degree of integration can be improved as compared with the one-transistor one-capacitor ferroelectric memory.
Operations of the simple matrix ferroelectric memory are now described with reference to FIGS. 61 and 62. Table 1 shows voltages applied to each cell 121 in reading/writing.
TABLE 1StandbyReadingWriting “1”Writing “0”Selected WL½ VccVcc0VccNon-Selected WL½ Vcc⅓ Vcc⅔ Vcc⅓ VccSelected BL½ Vcc0→FloatingVcc0Non-Selected BL½ Vcc⅔ Vcc⅓ Vcc⅔ Vcc
In a write operation, both ends of the ferroelectric capacitor 122 are at the same potential in a standby state. In order to write data “0”, the simple matrix ferroelectric memory applies a voltage Vcc to the word line WL while applying a voltage of 0 V to the bit line BL. At this time, the simple matrix ferroelectric memory applies the voltage Vcc to the ferroelectric capacitor 122, thereby making a transition to a point A shown in FIG. 62. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, for making a transition to “0” shown in FIG. 62. In order to write data “1”, the simple matrix ferroelectric memory applies the voltage 0 V to the word line WL while applying the voltage Vcc to the bit line BL. At this time, the simple matrix ferroelectric memory applies a voltage −Vcc to the ferroelectric capacitor 122, thereby making a transition to a point B in FIG. 62. Thereafter the simple matrix ferroelectric memory sets both ends of the ferroelectric capacitor 122 to the same potential, for making a transition to “1” shown in FIG. 62.
In a read operation, the simple matrix ferroelectric memory first precharges the bit line BL to 0 V. Then, the simple matrix ferroelectric memory raises the word line WL to the voltage Vcc. This voltage is Vcc capacitively divided by a capacitance CFE of the ferroelectric capacitor 122 and a parasitic capacitance CBL of the bit line BL. The capacitance CFE of the ferroelectric capacitor 122 can be approximated as a capacitance C0 or C1 depending on held data. Therefore, the potential of the bit line BL is expressed as follows:V0={C0/(C0+CBL)}×Vcc  (1)V1={C1/(C1+CBL)}×Vcc  (2)
The equation (1) expresses the potential V0 of the bit line BL when holding data “0”, and the equation (2) expresses the potential V1 of the bit line BL when holding data “1”.
The simple matrix ferroelectric memory determines the potential difference between the bit line potentials V0 and V1 expressed in the above equations (1) and (2) respectively with a read amplifier, thereby reading the data. Data of the memory cell 121 is destroyed in this data reading and hence the simple matrix ferroelectric memory performs a write operation (restore operation) responsive to read data after the data reading.
In the simple matrix ferroelectric memory, however, data of non-selected cells disadvantageously disappear due to disturbance. In other words, it follows that a voltage ⅓Vcc is applied to all non-selected memory cells in writing and reading. As shown in FIG. 63, therefore, the quantity of polarization is decreased due to hysteresis characteristics of a ferroelectric substance, to result in disappearance of data.
The one-transistor ferroelectric memory is now described with reference to FIGS. 64 to 67. As shown in FIG. 64, the memory cell 131 of the one-transistor ferroelectric memory is formed by connecting a ferroelectric capacitor 132 to the gate of a MOS transistor 133. In the one-transistor ferroelectric memory, an end of the ferroelectric capacitor 132 is connected to a word line WL, while the other end thereof is connected to the gate of the MOS transistor 133 forming a cell transistor. In the one-transistor ferroelectric memory, the threshold voltage of the MOS transistor 133 varies with the direction of polarization of the ferroelectric capacitor 132, to change a memory cell current. The one-transistor ferroelectric memory reads data by determining this change of the memory cell current. The one-transistor ferroelectric memory reads data by detecting the memory cell current, and hence the capacitance of the ferroelectric capacitor 132 may not be increased to some extent in consideration of the bit line capacitance, dissimilarly to the one-transistor one-capacitor ferroelectric memory shown in FIG. 60. Therefore, the ferroelectric capacitor 132 can be reduced in size so that the one-transistor ferroelectric memory is suitable for refinement.
Operations of the one-transistor ferroelectric memory are now described. In a standby state, every word line WL, every bit line BL and every source line SL are at 0 V. In a write operation, the one-transistor ferroelectric memory applies a step-up voltage Vpp to the word line WL, in order to write data “0”. At this time, the one-transistor ferroelectric memory applies a potential capacitively divided with the gate capacitance of the MOS transistor 133 to the ferroelectric capacitor 132, thereby making a transition to a point A shown in FIG. 65 despite an initial state. Thereafter the one-transistor ferroelectric memory returns the word line WL to 0 V, for making a transition to data “0” shown in FIG. 65. In order to write data “1”, the one-transistor ferroelectric memory applies a voltage of 0 V to the word line WL while applying the step-up voltage Vpp to the bit line BL. In this case, the one-transistor ferroelectric memory applies a voltage −Vcc to the ferroelectric capacitor 132, thereby making a transition to a point B shown in FIG. 65. Thereafter the one-transistor ferroelectric memory returns the bit line BL to 0 V, thereby making a transition to data “1” shown in FIG. 65.
In a read operation, the one-transistor ferroelectric memory raises the word line WL to a voltage Vr causing no polarization inversion. Thus, the gate voltage of the cell transistor (MOS transistor) 133 varies with a write state. A current flowing through the cell transistor 133 varies with change of the gate voltage of the cell transistor 133, and the one-transistor ferroelectric memory reads the current difference through the bit line BL. The one-transistor ferroelectric memory, which may read not potential difference resulting from capacitive coupling between the ferroelectric capacitor 132 and a bit-line capacitance but the current of the cell transistor 133, requires no polarization inversion in reading. Therefore, the one-transistor ferroelectric memory is capable of non-destructive reading.
However, the one-transistor ferroelectric memory also has the problem of disturbance of non-selected cells, similarly to the aforementioned simple matrix ferroelectric memory. Further, data changes by the so-called reverse bias retention resulting from a continuous reverse bias state to the ferroelectric capacitor 132. When the one-transistor ferroelectric memory applies the step-up voltage Vpp to the word line WL thereby writing data as shown in FIG. 66 and thereafter returns to the standby state in data writing, a potential opposite to polarization is continuously applied as shown in FIG. 67. Therefore, the data holding time is disadvantageously reduced.
As hereinabove described, it is difficult to refine the conventional DRAM and the conventional flash memory, and hence a memory cell system allowing a higher degree of integration is demanded. While the one-transistor ferroelectric memory and the simple matrix ferroelectric memory can be high integrated, data of non-selected cells disappear due to disturbance or data change by reverse bias retention resulting from a continuous reverse bias state, as hereinabove described. Thus, it is difficult to put the conventional one-transistor and simple matrix ferroelectric memories into practice.